SCHEDULE: NOV 16-22, 2013
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An Early Performance Evaluation of Many Integrated Core Based SGI Rackable Computing System
SESSION: Application Performance Characterization
EVENT TYPE: Papers
TIME: 3:30PM - 4:00PM
SESSION CHAIR: Yao Zhang
AUTHOR(S):Subhash Saini, Haoqiang Jin, Dennis Jespersen, Huiyu Feng, Jahed Djomehri, William Arasin, Robert Hood, Piyush Mehrotra, Rupak Biswas
ROOM:405/406/407
ABSTRACT:
Intel recently introduced the Xeon Phi coprocessor based on the Many Integrated Core architecture featuring 60 cores with a peak performance of 1.0 Tflop/s. NASA has deployed a 128-node SGI Rackable system where each node has two Intel Xeon E2670 8-core Sandy Bridge processors along with two Xeon Phi 5110P coprocessors. We have conducted an early performance evaluation of the Xeon Phi. We used microbenchmarks to measure the latency and bandwidth of memory and interconnect, I/O rates, and the performance of OpenMP directives and MPI functions. We also used OpenMP and MPI versions of the NAS Parallel Benchmarks along with two production CFD applications to test four programming modes: offload, processor native, coprocessor native and symmetric (processor plus coprocessor). In this paper we present preliminary results based on our performance evaluation of various aspects of a Phi-based system.
Chair/Author Details:
Yao Zhang (Chair) - Argonne National Laboratory
Subhash Saini - NASA Ames Research Center
Haoqiang Jin - NASA Ames Research Center
Dennis Jespersen - NASA Ames Research Center
Huiyu Feng - SGI Inc
Jahed Djomehri - Computer Science Corp.
William Arasin - Computer Science Corp.
Robert Hood - Computer Science Corp.
Piyush Mehrotra - NASA Ames Research Center
Rupak Biswas - NASA Ames Research Center
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The full paper can be found in the ACM Digital Library