SCHEDULE: NOV 16-22, 2013

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Tera-Scale 1D FFT with Low-Communication Algorithm on Intel Xeon Phi Coprocessors

SESSION: Performance Analysis of Applications at Large Scale

EVENT TYPE: Papers

TIME: 10:30AM - 11:00AM

SESSION CHAIR: Darren J. Kerbyson

AUTHOR(S):Jongsoo Park, Ganesh Bikshandi, Karthikeyan Vaidyanathan, Ping Tak Peter Tang, Pradeep Dubey, Daehyun Kim

ROOM:201/203

ABSTRACT:
This paper demonstrates the first tera-scale performance of Intel Xeon Phi coprocessors on 1D FFT computations. Applying a disciplined performance programming methodology of sound algorithm choice, valid performance model, and well-executed optimizations, we break the tera-flop mark on a mere 64 nodes of Xeon Phi and reach 6.7 TFLOPS with 512 nodes, which is 1.5x than achievable on a same number of Intel Xeon nodes. It is a challenge to fully utilize the compute capability presented by many-core wide-vector processors for bandwidth-bound FFT computation. We leverage a new algorithm, Segment-of-Interest FFT, with low inter-node communication cost, and aggressively optimize data movements in node-local computations, exploiting caches. Our coordination of low communication algorithm and massively parallel architecture for scalable performance is not limited to running FFT on Xeon Phi; it can serve as a reference for other bandwidth-bound computations and for emerging HPC systems that are increasingly communication limited.

Chair/Author Details:

Darren J. Kerbyson (Chair) - Pacific Northwest National Laboratory

Jongsoo Park - Intel Corporation

Ganesh Bikshandi - Intel Corporation

Karthikeyan Vaidyanathan - Intel Corporation

Ping Tak Peter Tang - Intel Corporation

Pradeep Dubey - Intel Corporation

Daehyun Kim - Intel Corporation

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The full paper can be found in the ACM Digital Library