SCHEDULE: NOV 16-22, 2013

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Location-Aware Cache Management for Many-Core Processors with Deep Cache Hierarchy

SESSION: Memory Hierarchy

EVENT TYPE: Papers

TIME: 2:00PM - 2:30PM

SESSION CHAIR: Mark Gardner

AUTHOR(S):Jongsoo Park, Richard M. Yoo, Daya S. Khudia, Christopher J. Hughes, Daehyun Kim

ROOM:405/406/407

ABSTRACT:
As cache hierarchies become deeper and the number of cores on a chip increases, managing caches becomes more important for performance and energy. However, current hardware cache management policies do not always adapt optimally to the applications behavior: e.g., caches may be polluted by data structures whose locality cannot be captured by the caches, and producer-consumer communication incurs multiple round trips of coherence messages per cache line transferred. We propose load and store instructions that carry hints regarding into which cache(s) the accessed data should be placed. Our instructions allow software to convey locality information to the hardware, while incurring minimal hardware cost and not affecting correctness. Our instructions provide a 1.16x speedup and a 1.96x energy efficiency boost, on average, according to simulations on a 64-core system with private L1 and L2 caches. With a large shared L3 cache added, the benefits increase, providing 1.33x energy reduction on average.

Chair/Author Details:

Mark Gardner (Chair) - Virginia Tech

Jongsoo Park - Intel Corporation

Richard M. Yoo - Intel Corporation

Daya S. Khudia - University of Michigan

Christopher J. Hughes - Intel Corporation

Daehyun Kim - Intel Corporation

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The full paper can be found in the ACM Digital Library