SCHEDULE: NOV 16-22, 2013
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Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing
SESSION: Memory Hierarchy
EVENT TYPE: Papers
TIME: 1:30PM - 2:00PM
SESSION CHAIR: Mark Gardner
AUTHOR(S):Richard Yoo, Christopher Hughes, Konrad Lai, Ravi Rajwar
Intel has recently introduced Intel Transactional Synchronization Extensions (Intel TSX) in the Intel 4th Generation Core Processors. With Intel TSX, a processor can dynamically determine whether threads need to serialize through lock-protected critical sections. In this paper, we evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads, and demonstrate that applying Intel TSX to these workloads can provide significant performance improvements. On a set of real-world HPC workloads, applying Intel TSX provides an average speedup of 1.41x. When applied to a parallel user-level TCP/IP stack, Intel TSX provides 1.31x average bandwidth improvement on network intensive applications. We also demonstrate the ease with which we were able to apply Intel TSX to the various workloads.
Mark Gardner (Chair) - Virginia Tech
Richard Yoo - Intel Corporation
Christopher Hughes - Intel Corporation
Konrad Lai - Intel Corporation
Ravi Rajwar - Intel Corporation
The full paper can be found in the ACM Digital Library