SCHEDULE: NOV 16-22, 2013
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Exploring DRAM Organizations for Energy-Efficient and Resilient Exascale Memories
SESSION: Memory Resilience
EVENT TYPE: Papers
TIME: 11:00AM - 11:30AM
SESSION CHAIR: Scott Pakin
AUTHOR(S):Bharan Giridhar, Michael Cieslak, Deepankar Duggal, Ronald Dreslinski, Hsing Min Chen, Robert Patti, Betina Hold, Chaitali Chakrabarti, Trevor Mudge, David Blaauw
The power target for exascale supercomputing is 20MW, with about 30% budgeted for the memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the large number of memory chips (>10M) required will result in crippling failure rates. Although specialized DRAM memories have been reorganized to reduce power through 3D-stacking or row buffer resizing, their implications on fault tolerance have not been considered. We show that addressing reliability and energy is a co-optimization problem involving tradeoffs between error correction cost, access energy and refresh power; reducing the physical page size to decrease access energy increases the energy/area overhead of error resilience. Additionally, power can be reduced by optimizing bitline lengths. The proposed 3D-stacked memory uses a page size of 4kb and consumes 5.1pJ/bit based on simulations with NEK5000 benchmarks. Scaling to 100PB, the memory consumes 4.7MW at 100PB/s which, while well within the total power budget (20MW), is also error-resilient.
Scott Pakin (Chair) - Los Alamos National Laboratory
Bharan Giridhar - University of Michigan
Michael Cieslak - University of Michigan
Deepankar Duggal - University of Michigan
Ronald Dreslinski - University of Michigan
Hsing Min Chen - Arizona State University
Robert Patti - Tezzaron Semiconductor
Betina Hold - ARM Ltd.
Chaitali Chakrabarti - Arizona State University
Trevor Mudge - University of Michigan
David Blaauw - University of Michigan
The full paper can be found in the ACM Digital Library