SC13 Home > SC13 Schedule > SC13 Presentation - Quantifying the Dominance of Leakage Energy in Large-Scale System Caches

SCHEDULE: NOV 16-22, 2013

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Quantifying the Dominance of Leakage Energy in Large-Scale System Caches

SESSION: Research Poster Reception

EVENT TYPE: Posters, Electronic Posters, and Education Posters

TIME: 5:15PM - 7:00PM

AUTHOR(S):Aditya M. Deshpande, Jeffrey T. Draper

ROOM:Mile High Pre-Function

Energy consumption is becoming a critical metric in the design and use of large-scale high-performance systems. With large on-chip caches and advances in chip fabrication technologies, on-chip caches account for a large proportion of total leakage power losses. In this work, we quantify on-chip cache leakage-power losses across a wide set of parallel applications and compare the leakage and dynamic energy consumption for various levels of on-chip caches. Our scheme profiles an application to measure cache accesses in order to estimate the energy consumption for various levels of caches. Our study indicates that for various levels of cache, leakage-energy consumption significantly dominates dynamic-energy consumption, and this trend of leakage domination in on-chip caches is expected to increase with every new generation of semiconductor process. Our study indicates that the problem of leakage in on-chip caches cannot be neglected in attacking the energy barrier for building extreme-scale systems.

Chair/Author Details:

Aditya M. Deshpande - University of Southern California

Jeffrey T. Draper - University of Southern California

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