SC13 Home > SC13 Schedule > SC13 Presentation - Compiling Affine Loop Nests for Distributed-Memory Parallel Architectures

SCHEDULE: NOV 16-22, 2013

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Compiling Affine Loop Nests for Distributed-Memory Parallel Architectures

SESSION: Parallel Programming Models and Compilation

EVENT TYPE: Papers

TIME: 11:30AM - 12:00PM

SESSION CHAIR: Ganesh Gopalakrishnan

AUTHOR(S):Uday Bondhugula

ROOM:405/406/407

ABSTRACT:
We present new techniques for compilation of arbitrarily nested loops with affine dependencies for distributed-memory parallel architectures. Our framework is implemented as a source-level transformer that uses the polyhedral model, and generates parallel code with communication expressed with the Message Passing Interface (MPI) library. Compared to all previous approaches, ours is a significant advance either (1) with respect to the generality of input code handled, or (2) efficiency of communication code, or both. We provide experimental results on a cluster of multicores demonstrating its effectiveness. In some cases, code we generate outperforms manually parallelized codes, and in another case is within 25% of it. To the best of our knowledge, this is the first work reporting end-to-end fully automatic distributed-memory parallelization and code generation for input programs and transformation techniques as general as those we allow.

Chair/Author Details:

Ganesh Gopalakrishnan (Chair) - University of Utah

Uday Bondhugula - Indian Institute of Science

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The full paper can be found in the ACM Digital Library